The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to alignment through topography on an intermediate component for memory device patterning.
Integrated circuit chips are fabricated one level at a time. The levels include, for example, diffusions, gates, metal lines, insulation, isolation, and contacts. The structures on these levels must be precisely positioned so that the finished chip has properly positioned structures. The step of positioning a level with respect to a previously formed level is called alignment.
Alignment of patterned materials involves manual or automatic selection of alignment targets. The alignment targets typically include “alignment marks” that a recognition system uses to learn a position of the part or material subject to examination. A user or computer then provides a region of interest (ROI) by moving to the selected location, while the software records this coordinate. Alternatively, a coordinate relative to some known reference point (e.g., center of the part) is indicated by the software. Once the setup is completed (i.e., after the alignment marks are recorded), the optical system aligns and moves to a ROI on the part for measurement or inspection.